![]() ![]() However, I don't see any place where I send more than one signal to my first 4-Bit CLA instance in the 8-Bit CLA module. The second 4 bits add just fine, though.Īfter doing some research, I found out that X's are displayed in Verilog when a wire has more than one driver (source of the signal?). So the problem is, in my simulations of the testbench (I use ModelSim), the first 4 bits of the Sum (which correspond to the first 4-bit CLA instance in the 8-bit CLA module) are given as X in the Wave page. I wrote a basic testbench to test my code: module CLA_TB() The two 4-bit CLA blocks that make up the 8-bit CLAĬLA4Bit block1(A, B, carryIn, c3, p3, g3, Sum) ĬLA4Bit block2(A, B, c3, c7, p7, g7, Sum) Wires for the carry of the first block (c3) and the Wires for the generate of the first 4-bit block (g3) Wires for the propagate of the first 4-bit block (p3) Module CLA8Bit(A, B, carryIn, carryOut, Sum) Module CLA4Bit(A, B, carryIn, carryOut, PG, GG, Sum) Īssign C = G | (P & G) | (P & P & C) Īssign C = G | (P & G) | (P & P & G) | (P & P & P & C) Īssign GG = G | (P & G) | (P & P & G) | (P & P & P & G) I'll provide my code, then an explanation of the problem I'm having. Basically, the way I implemented it is I use 2 4-bit CLA "blocks" to create the 8-bit CLA. I'm trying to put together an 8-bit Carry Lookahead Adder as a step toward building a 64-bit CLA. ![]()
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